Juan Touriño

Full Professor of Computer Engineering

(Catedrático de Universidad - Área de Arquitectura y Tecnología de Computadores)

ORCID ResearcherID (Publons)

Email: juan@udc.es
Office: 1.14, Faculty of Informatics
Phone: +34-981167000 Fax: +34-981167160

Mailing Address:
Department of Computer Engineering
Faculty of Informatics
University of A Coruña
Campus de Elviña s/n, 15071 A Coruña, Spain

Member of CITIC (Research Center on Information and Communication Technologies)

Short Bio

Education

B.S. , M.S. (1993) in Informatics, University of A Coruña
Ph.D. (1998) in Computer Engineering, University of A Coruña

Teaching

Computer Architecture - Concurrency and Parallelism (B.S. in Informatics)
Advanced Parallel Processing (B.S. in Data Science & Engineering)
High Performance Architectures - Parallel Programming (Master in High Performance Computing)
Interuniversity PhD Program in Information Technology Research

Research
Co-PI of the Computer Architecture Group at the University of A Coruña

Coordinator of the Galician Network on Cloud and Big Data Technologies for HPC

Member of HiPEAC, European Network of Excellence on High Performance and Embedded Architecture and Compilation (EU H2020 Programme)

My primary research interest is in the area of High Performance Computing (HPC) at all levels: architectures, operating systems, networks, compilers, programming languages/libraries, algorithms and applications. My research lines are:

Big Data and cloud computing:

Performance evaluation of Big Data frameworks with BDEv
Performance monitoring and profiling of Big Data frameworks and applications with BDWatchdog
Serverless container platform for automatic rescaling of Big Data workloads, including energy capping policies
Optimization of MapReduce Big Data processing with Flame-MR

Parallel algorithms, libraries and applications (Bioinformatics applications: HSRA, MarDRe, MSAProbs-MPI, SMusket) (AI applications: Fast-mRMR) (UPCBLAS Library)
Compilers and architectures for high performance computing (Tejas KNL)
Low-latency communications for high performance computing (Speedus and FastMPJ)
Performance evaluation and information gathering of parallel programming languages and architectures (UPC Benchmarks, Servet Benchmark Suite, jhwloc)
Fault tolerance: checkpointing of parallel codes (CPPC Project)
Management of parallel/distributed systems (AdCIM Project)

My other research interest is Geographic Information Systems (GIS) applied to land management and weather forecast (also cross-cutting with HPC)

Technology Transfer
Co-Founder of the start-up Torus Software Solutions (solutions in the areas of Big Data, HPC and microservices)

Publications (partly included in the DBLP Server)

Professional Service IEEE Access, Associate Editor (2018-)

Past Students

Last Update: 08-Jul-2022