Date: 2002/06/12

I have made a few extensions to the language and the runtime system.
Now SESC allows to specify the number of registers and latencies for the different execution units. This means we can now simulate processors with different clock rates.
(Almost) everything works, the birds sing, the sun shines, the world is beautiful...

Date: 2002/05/21

Simulator improved with many new processor details. As a result the timings are much more realistic, but of course the simulator is slightly slower. We are working (successfully) on that.
CCFlex compiler implements some optimizations. Typical speed ups of about 10% are achieved.
We have chosen as main processor of our system the Power4 processor at 1.6 GHz, one of the most powerful processors available.
The IMO libraries have been improved too. The results are pretty good :-)
Improvements in the runtime system related to polling periodically the chips.

Date: 2002/04/18

Simulator has reached stability. Still, network yet to be integrated.
Now instrumenting and benchmarking...
SESC, our simulator, has now its own WWW page.

Date: 2002/03/11

Compiler ported to generate code for SESC FlexRAM OS and Runtime libraries.
Small tests spawning several threads both in the PHost and the PArrays successful.
Simple OS extension to provide FIFO-like scheduling for the PHost threads (Joe's internal scheduler always seems to alternate between the last two spawned ones...).
Other OS/Runtime library notes:
  • Wait algorithm for spawned threads based in yield to next thread in FIFO. This means that the CPU wait is always busy. Think how to speed up simulation suspending threads, removing them from the queue, activating them, etc.
  • Yet to try/debug local heap management runtime library for PArrays.

Date: 2002/03/03

First execution of the system including spawning a task on a PArray and getting the resuls.
Core OS Interruption SW handlers and kernel working.
The improvements in the internal structure of the simulator have speeded it up about 30% since January.

Date: 2002/02/13

Threads completely removed from the backend: now we only use callbacks.
Adding function to interrupt processor resuming threads from the backend.
HUGE change decided in FlexRAM architecture: Mesh added, PMem removed.

Date: 2002/01/31

Backend internals completely modified to simulate real lock-up free cache with a given number of MSHRs.
Write buffer between each cache and its lower level adapted to the write policy (WT/WB) that stalls when full and allows reads to bypass writes.
Interaction of write buffer stall with cache stall due to blocking may have to be further studied.

Date: 2002/01/21

Cache flush operation implemented.

Date: 2002/01/10

TLB, OS with two-level page table implemented.

Date: 2001/12/18

Improvements to FlexRAM memory backend:
  • Check of maximum number of simultaneous misses implemented.
  • Several performance improvements implemented.
  • Statistics collection/storage adapted to SESC.

Date: 2001/12/14

FlexRAM memory backend ported to SESC. Future work/notes:
  • No coherence protocol (FlexRAM has no coherence protocol, so...).
  • Implement sync/async cache flush.

Date: 2001/12/07

FlexRAM compiler kernel implementing FXTASK pragmas finished.
Native version using pthreads simulates processor control in sync/async mode.
Agreement to port the current FlexRAM memory backend for MINT/SMT to the new SESC simulator (may be also useful for M3T).
Work log started.