OUR RESEARCH LINES:

Automatic generation of parallel code: This research line addresses the automatic parallelization of sequential programs. The focus is on the development of compiler techniques to convert a sequential program into a concurrent program to be executed in modern multi-core and many-core architectures. We are working on the development of advanced program analyses to discover the parallelism implicit in sequential programs and the development of code transformation techniques to build the most efficient parallel version of a sequential program.

Iterative Optimization: We are working on the iterative optimization of codes on heterogeneous architectures including GPUs and/or CPUs. Iterative optimization allows generating a huge number of optimized versions of the same application and selecting the fastest version for a given architecture by means of analytical models, heuristics or the execution of the real code.

Our group designs and builds tools (Servet) and libraries (HTA, UPCBLAS) to improve the productivity of programmers, particularly in the development of parallel applications. Servet is a portable suite of benchmarks to obtain the most relevant hardware parameters to support the automatic optimization of applications on multicore clusters. The Hierarchically Tiled Array or HTA data type is a class designed to facilitate the writing of programs based on tiles in object-oriented languages. HTAs allow exploiting locality as well as to express parallelism with much less effort than other approaches. UPCBLAS is a parallel numerical library for dense matrix computation using the PGAS (Partitioned Global Address Space) UPC (Unified Parallel C) language. The popularity of PGAS languages has increased during the last years thanks to their high programmability and performance especially on hierarchical architectures such as multicore clusters.

Our proposals, which cover distributed, shared and hybrid memory systems, lead to codes which are better structured, more readable and easier to maintain than those built using standard tools, while the performance is very similar. Much of this research has been performed in close collaboration with leading universities such as the University of Illinois at Urbana-Champaign or first level companies such as HP and IBM.

Systems intended for the execution of long-running parallel applications should provide fault tolerant capabilities, since the probability of failure increases with the execution time and the number of nodes. Checkpointing and rollback recovery is one of the most popular techniques to provide fault-tolerance support. We have developed CPPC (ComPiler for Portable Checkpointing), an application-level checkpointing tool for message-passing applications designed with special focus on portability.

Currently we are exploring the possibility of implementing malleability of MPI applications as an extension to the CPPC tool, so that the final approach enables transparent reconfiguration during the application’s execution.

In this field we are working in the development of tools that allow the automatic or semi-automatic implementation of algorithms on a GPU. Additionally, another objective is to develop high-level libraries for multi-GPU systems focused on providing simple yet efficient communication among the different GPUs. All our research is centred in providing solutions based on the main programming languages in these platforms, such as OpenCL and Cuda.

We are working on low latency Java communication middleware in high-speed cluster networks, such as 10/40 Gigabit Ethernet and InfiniBand. The developed middleware supports message-passing communications (Fast MPJ), as well as speeds up communications in a user-transparent way (Java Fast Sockets). The main objective is the reduction of the response time of parallel and distributed Java applications, key in several areas such as high frequency financial trading.

The main goal of this research line is to achieve an efficient processing of complex graphical models, such as surface subdivision, parametric surfaces and hybrid terrain representation. We put special emphasis on the development of interactive real-time processing, efficiently exploiting the cutting-edge hardware that can be found in current computer systems: multicore CPUs and GPUS (Graphics Processing Unit).

Another relevant topic within this research field is the photo-realistic rendering of synthesis images, using both physically-based illumination models, advanced texture mapping and transparency effects.

We have participated in the development of SESC, a research microarchitecture simulator used worldwide.  The group also innovates in this field proposing new memory hierarchy architectures as well as management policies with the aim of improving the execution times and reducing the power consumption of applications both in single core and multicore systems.

In terms of energy efficiency, the gap between microprocessors and application-specific circuits is steadily increasing. Hardware acceleration is, therefore, a powerful way of reducing costs and achieving green computing.

Whereas the cost of designing and manufacturing application-specific circuits is high, a number of alternative platforms are now available, such as FPGAs, structured ASICs or ASIPs. Most of the new platforms have been developed for embedded systems, where they have already enabled fast and low-power computing.

This research line explores the potential of mapping common tasks onto hardware accelerators in order to improve energy efficiency, speed-up processing and even reduce the amount of hardware required. The main application scenarios include high-performance computing, Software-as-a-Service and Web 2.0, where a large number of servers may share a reduced number of accelerators for offloading the most demanding tasks.

We have developed a unified analytical framework to predict accurately the cache behaviour. The framework, which provides its estimations in less than one second, only requires as input the source code and the memory hierarchy configuration. Our approach is fully automatable and may be used in a compiler. The framework has been used successfully for guiding complex compiler optimizations such as tile size selection as well as to predict the worst-case execution time for real-time systems.