High performance microprocessors: / Computer Architecture Group.

+ High performance microprocessors:

- Computer microarchitecture design:

We have participated in the development of SESC, a research microarchitecture simulator used worldwide.  The group also innovates in this field proposing new memory hierarchy architectures as well as management policies with the aim of improving the execution times and reducing the power consumption of applications both in single core and multicore systems.

 

 

- Hardware accelerator design for multimedia and energy-efficient computing

In terms of energy efficiency, the gap between microprocessors and application-specific circuits is steadily increasing. Hardware acceleration is, therefore, a powerful way of reducing costs and achieving green computing. Whereas the cost of designing and manufacturing application-specific circuits is high, a number of alternative platforms are now available, such as FPGAs, structured ASICs or ASIPs. Most of the new platforms have been developed for embedded systems, where they have already enabled fast and low-power computing. This research line explores the potential of mapping common tasks onto hardware accelerators in order to improve energy efficiency, speed-up processing and even reduce the amount of hardware required. The main application scenarios include high-performance computing, Software-as-a-Service and Web 2.0, where a large number of servers may share a reduced number of accelerators for offloading the most demanding tasks.

 

- Analytical modelling and performance prediction of the memory hierarchy of computer systems

We have developed a unified analytical framework to predict accurately the cache behaviour. The framework, which provides its estimations in less than one second, only requires as input the source code and the memory hierarchy configuration. Our approach is fully automatable and may be used in a compiler. The framework has been used successfully for guiding complex compiler optimizations such as tile size selection as well as to predict the worst-case execution time for real-time systems.

 

 

 

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